NMOS and CMOS Logic Circuits¶

Possible Exam Questions¶

Device-Level NMOS and CMOS Logic¶

NMOS Logic¶

NMOS Logic Definition¶

NMOS logic is a family of digital circuits built using only N-channel MOSFETs. In NMOS logic, the pull-down network (active logic) uses enhancement-mode NMOS transistors, while the pull-up (load) uses either a depletion-mode NMOS transistor, a resistor, or an enhancement-mode NMOS. NMOS logic preceded CMOS and was dominant in early microprocessors (Intel 8080, 8085).

NMOS Inverter with Depletion Load¶

The most common NMOS inverter uses a depletion-mode NMOS as the load (gate tied to source, always ON) and an enhancement-mode NMOS as the driver (controlled by input).

On an IC a large-value load resistor is impractical to fabricate (it would occupy an enormous area), so the resistor is replaced by a MOSFET acting as an active load — either a depletion-mode NMOS (gate tied to source) or an enhancement-mode NMOS (gate and drain tied to \(V_{DD}\)). Its channel ON-resistance provides the required pull-up. An enhancement load can only pull the output up to \(V_{DD}-V_T\) (a weak 1 — see below), so the depletion load is preferred.

Operation:

Limitation of NMOS logic: There is always a DC current path from \(V_{DD}\) to ground when the output is LOW (both load and driver are ON). This means NMOS logic has significant static power dissipation, which limits integration density.

NMOS NAND Gate¶

Uses series-connected enhancement NMOS transistors in the pull-down path, sharing one depletion-mode load. Output goes LOW only when all inputs are HIGH (all series transistors ON).

NMOS NOR Gate¶

Uses parallel-connected enhancement NMOS transistors in the pull-down path, sharing one depletion-mode load. Output goes LOW when any input is HIGH (any parallel transistor ON).

CMOS Logic¶

CMOS Logic Definition¶

CMOS (Complementary Metal-Oxide-Semiconductor) logic uses complementary pairs of P-channel and N-channel MOSFETs. In every CMOS gate, there is a PMOS pull-up network (connects output to \(V_{DD}\)) and an NMOS pull-down network (connects output to ground). The two networks are complementary — when one is ON, the other is OFF. This means there is no direct DC path from \(V_{DD}\) to ground in either logic state, resulting in near-zero static power dissipation. This is the single most important advantage of CMOS.

MOSFETs as Switches — Strong and Weak Logic Levels¶

Inside a logic gate a MOSFET behaves as a voltage-controlled switch, with the gate-to-source voltage \(V_{GS}\) as the control:

• NMOS: ON (closed) when \(V_{GS} > V_{Tn}\); OFF (open) when \(V_{GS} < V_{Tn}\).
• PMOS: the threshold is negative — ON when \(V_{SG} > \lvert V_{Tp}\rvert\) (a LOW gate); OFF when the gate is HIGH.

The key to CMOS is that each device passes one logic level well ("strong") and the other poorly ("weak"):

• An NMOS passes a strong 0 but a weak 1. When it tries to pull a node up, the rising source voltage shrinks \(V_{GS}\); conduction stops once \(V_{GS}=V_{Tn}\), so the output cannot rise above \(V_{DD}-V_{Tn}\).
• A PMOS passes a strong 1 but a weak 0. When it tries to pull a node down, conduction stops once \(V_{SG}=\lvert V_{Tp}\rvert\), so the output cannot fall below \(\lvert V_{Tp}\rvert\).

This is exactly why CMOS uses a PMOS pull-up (delivers a strong 1) and an NMOS pull-down (delivers a strong 0). The complementary pair gives rail-to-rail (full-swing) output — \(0\,\text{V}\) to \(V_{DD}\) — and hence the maximum noise margin, the decisive advantage over NMOS-only or PMOS-only logic.

CMOS Inverter — The Fundamental CMOS Gate¶

The CMOS inverter consists of one PMOS (pull-up) and one NMOS (pull-down) transistor.

Operation:

In both stable states, one transistor is always OFF → no static current → zero static power dissipation.

Current flows only during the brief transition when both transistors are momentarily ON.

CMOS Inverter — Voltage Transfer Characteristic (VTC)¶

The VTC shows the relationship between \(V_{in}\) and \(V_{out}\). For a symmetric CMOS inverter (matched NMOS and PMOS):

• Switching threshold: \(V_{th} = V_{DD}/2\) (midpoint transition)
• Full output swing: Output swings between \(0\,\text{V}\) and \(V_{DD}\) (rail-to-rail)
• High noise margins: \(NM_H = NM_L \approx V_{DD}/2 - V_{th(\text{transistor})}\)

The VTC has five operating regions as \(V_{in}\) sweeps from 0 to \(V_{DD}\). The sharp transition in the middle gives CMOS its excellent noise immunity.

The paired characteristics below make the technology trade-off explicit: the depletion-load NMOS switching point and LOW level depend on the driver/load ratio and a DC path remains when the driver conducts, whereas complementary CMOS gives rail-to-rail levels, a near-mid-supply switching point, and wide noise margins with negligible static current.

Transfer curve: \(V_{out}\) stays near \(V_{DD}\) for small \(V_{in}\), drops sharply at the switching threshold \(V_{in}\approx V_{DD}/2\), and settles near 0 for large \(V_{in}\) — giving rail-to-rail swing and large noise margins.

CMOS NAND Gate¶

Structure:

• PMOS pull-up network: Two PMOS transistors in parallel (output goes HIGH if any input is LOW → any PMOS turns ON)
• NMOS pull-down network: Two NMOS transistors in series (output goes LOW only when all inputs are HIGH → all NMOS turn ON)

Truth Table (2-input CMOS NAND):

CMOS Rule for gate construction:

• NAND → NMOS in series, PMOS in parallel
• NOR → NMOS in parallel, PMOS in series

CMOS NOR Gate¶

Structure:

• PMOS pull-up network: Two PMOS transistors in series (output goes HIGH only when all inputs are LOW → all PMOS turn ON)
• NMOS pull-down network: Two NMOS transistors in parallel (output goes LOW if any input is HIGH → any NMOS turns ON)

General CMOS Gate Synthesis (PUN/PDN Duality)¶

Every static CMOS gate computes an inverting function \(Y=\overline{f}\) using two complementary networks driven by the same inputs:

• The pull-down network (PDN, NMOS) conducts — pulling \(Y\) to \(0\) — exactly when \(f=1\). Build it directly from \(f\): an AND (\(\cdot\)) becomes NMOS in series; an OR (\(+\)) becomes NMOS in parallel.
• The pull-up network (PUN, PMOS) is the dual of the PDN: wherever the PDN is in series the PUN is in parallel, and vice-versa. It conducts — pulling \(Y\) to \(V_{DD}\) — exactly when \(f=0\).

At any instant exactly one network conducts, so there is never a DC path from \(V_{DD}\) to ground. The method extends to any fan-in and any Boolean function:

• 3-input NAND \(Y=\overline{ABC}\): 3 NMOS in series (PDN) + 3 PMOS in parallel (PUN).
• 3-input NOR \(Y=\overline{A+B+C}\): 3 NMOS in parallel (PDN) + 3 PMOS in series (PUN).
• AND-OR-Invert (AOI) functions such as \(Y=\overline{AB+C}\) map their series/parallel groups directly, realising a whole complex gate in a single stage.

Inputs are assumed available in true form; any complemented input (\(\overline{A}\)) requires an extra inverter.

CMOS AND and OR Gates¶

Because a CMOS gate always has an inverting pull-up/pull-down structure, its natural gates are NOT, NAND and NOR. The non-inverting AND and OR are obtained by following the inverting gate with an inverter:

• AND = CMOS NAND + inverter (6 transistors)
• OR = CMOS NOR + inverter (6 transistors)

This is why, in CMOS, NAND/NOR are cheaper than AND/OR — the opposite of what beginners expect. Designers therefore prefer NAND/NOR-based logic.

CMOS Transmission Gate (Pass Gate)¶

A transmission gate (TG) places an NMOS and a PMOS in parallel, driven by complementary controls \(C\) and \(\overline{C}\). When \(C = 1\) both transistors are ON and the gate passes the signal with a full \(0\)-to-\(V_{DD}\) swing (the NMOS passes a strong 0, the PMOS a strong 1); when \(C = 0\) both are OFF and the path is open (high-impedance, Hi-Z).

The transmission gate is the building block of CMOS multiplexers, latches and XOR/XNOR gates.

CMOS XOR / XNOR Gate¶

XOR and XNOR are not primitive CMOS gates — they are compound functions:

Truth table:

Three common realisations:

1. Transmission-gate XOR — a compact, high-speed CMOS style using ~6–8 transistors (2 transmission gates + inverters). Preferred inside CMOS chips.
2. Universal-gate XOR — XOR built from four NAND gates (below); XNOR is then XOR followed by an inverter. Useful when only NAND gates are available.
3. Direct AOI (static CMOS) — realise the complementary function as one complex gate. Since \(\text{XOR}=0\) when \(A=B\), the PDN is \((A\!\cdot\!B)\parallel(\overline{A}\!\cdot\!\overline{B})\) and the dual PUN is \((A\parallel B)\) in series with \((\overline{A}\parallel\overline{B})\) — 8 transistors plus inverters for \(\overline{A},\overline{B}\).

The direct static-CMOS (AOI) realisations use 8 transistors each (inputs plus their complements). The NMOS pull-down encodes when the output is \(0\); the PMOS pull-up is its series↔parallel dual:

XOR/XNOR are the heart of parity generators/checkers, comparators and adders (the sum bit is \(S = A \oplus B \oplus C_{in}\)).

CMOS Power Dissipation¶

The load capacitance \(C_L\) comes from the input (gate) capacitance of the next stage plus interconnect wiring; every output transition (\(0\!\to\!1\) or \(1\!\to\!0\)) charges or discharges it through the conducting network, dissipating \(C_L V_{DD}^2\) per cycle. The short-circuit term arises because the finite input rise/fall time leaves both transistors briefly ON.

\(P_{dynamic}\) is proportional to \(V_{DD}^2\) — this is why reducing supply voltage is the most effective way to reduce CMOS power.

Logic Family Comparison¶

Model Answer — CMOS Inverter and Logic-Gate Realisation [10 marks]¶

Exam-ready answer

Complementary MOS (CMOS) logic uses a PMOS pull-up network (PUN) from \(V_{DD}\) to the output and a complementary NMOS pull-down network (PDN) from the output to ground. The PUN supplies a strong 1 and the PDN supplies a strong 0; in a stable state one network is OFF, so static power is ideally zero.

Inverter: the PMOS and NMOS gates share input \(A\), and their drains share output \(Y\).

\(A\)	PMOS	NMOS	\(Y\)
0	ON	OFF	\(V_{DD}\) (1)
1	OFF	ON	\(0\) (0)

Thus \(Y=\overline A\), with rail-to-rail output and no direct DC path in either stable state. Dynamic power is approximately \(P_{dyn}=\alpha C_LV_{DD}^{2}f\), where \(\alpha\) is switching activity, \(C_L\) is load capacitance (F), and \(f\) is frequency (Hz).

NAND: for \(Y=\overline{AB}\), place NMOS devices in series so both inputs must be HIGH to pull down; use the dual PUN with PMOS devices in parallel, so either LOW input pulls up.

NOR: for \(Y=\overline{A+B}\), place NMOS devices in parallel, so any HIGH pulls down; use PMOS devices in series, so only two LOW inputs pull up.

This is the general duality rule: construct the NMOS PDN from the condition \(f\) that should make the output LOW, replacing AND by series and OR by parallel; obtain the PMOS PUN by interchanging series and parallel. The resulting static gate computes \(Y=\overline f\).

Non-inverting gates: CMOS naturally gives NOT, NAND and NOR. Add one CMOS inverter after NAND to obtain AND,

\[Y=\overline{\overline{AB}}=AB,\]

and after NOR to obtain OR,

\[Y=\overline{\overline{A+B}}=A+B.\]

Each two-input AND or OR therefore needs six transistors: four in the NAND/NOR plus two in the inverter.

XOR:

\[ Y=A\oplus B=A\overline B+\overline AB, \]

which is 1 only for unequal inputs. It may be realised by four NAND gates, by a direct complementary AOI network, or efficiently with transmission gates. A transmission gate places NMOS and PMOS in parallel under complementary controls, combining the NMOS strong 0 with the PMOS strong 1 to pass a full-swing signal.

Example of operation: for a CMOS NAND with \(A=1,B=0\), the \(A\)-NMOS is ON but the series \(B\)-NMOS is OFF, so there is no path to ground; the \(B\)-PMOS is ON and pulls \(Y\) to \(V_{DD}\). Only \(A=B=1\) completes the PDN and gives 0.

CMOS gates provide high input impedance, wide noise margins, low static power and very high integration density. Leakage and switching power remain practical limitations, and excessive fan-in increases series resistance and propagation delay. These properties make CMOS the basis of processors, memories and system-on-chip logic.

Practice target: 16–18 minutes; draw inverter, NAND and NOR topologies and state the PUN/PDN duality before deriving AND, OR and XOR.

Model Answer — TTL, NMOS and CMOS Comparison [10 marks]¶

Mind Map¶