Flip-Flops¶

Exam-ready answer

A flip-flop is an edge-triggered bistable memory element that stores one bit. \(Q_n\) denotes the state before the active clock edge and \(Q_{n+1}\) the state after it. The four standard types differ in the input condition used to hold, set, reset or complement that state.

SR (set-reset) flip-flop

The constraint is essential: simultaneous set and reset can produce indeterminate/complement-inconsistent outputs when released.

JK flip-flop removes the SR forbidden case by making \(J=K=1\) a toggle:

It is versatile and is widely used in counters, but a level-triggered JK latch with a wide clock pulse can race when both inputs are 1.

D (data/delay) flip-flop has no ambiguous control combination; it copies the input only at the active edge:

It is therefore the natural element for registers, pipelines and sampled state storage. Between active edges, \(Q\) remains unchanged.

T (toggle) flip-flop holds for \(T=0\) and complements for \(T=1\):

With \(T=1\), one output cycle requires two clock edges, so it divides frequency by two and forms the basic counter stage.

Equation check: for JK with \(J=K=1\), \(Q_{n+1}=\overline Q_n+0=\overline Q_n\); for \(J=K=0\), \(Q_{n+1}=Q_n\). These verify toggle and hold directly from the characteristic equation.

Practice target: 16–18 minutes; draw all four symbols and reproduce every characteristic row/equation plus one application each.

Exam-ready answer

An SR flip-flop can hold, set and reset, but its \(S=R=1\) input is forbidden. A JK flip-flop requires the same first three operations and must toggle for \(J=K=1\). Output feedback can make the SR inputs depend on the present state so that they are never simultaneously 1.

Use two AND gates and connect

Because \(Q_n\overline{Q_n}=0\),

so the forbidden SR condition cannot occur. Substitute the feedback equations in the SR characteristic equation:

which is exactly the JK characteristic equation.

Operational verification

Thus when \(J=K=1\), the current state selects only one SR control: \(Q_n=0\) activates \(S\), while \(Q_n=1\) activates \(R\). The output complements on the active clock event.

Excitation check: desired transition \(0\to1\) needs \(J=1\) and \(K\) is don't-care; \(1\to0\) needs \(K=1\) and \(J\) is don't-care. The feedback network automatically translates these requirements into legal SR excitations.

The conversion must be clocked. If the underlying element is a level-sensitive SR latch and the active clock pulse is wider than the propagation delay, \(J=K=1\) can make the output toggle repeatedly through the feedback path, producing race-around. A master-slave pair or an edge-triggered SR implementation permits only one state transfer per clock and gives a practical JK flip-flop.

Practice target: 16–18 minutes; draw both feedback gates, prove \(SR=0\), derive the JK equation and verify all four JK operations.

Exam-ready answer

Race-around occurs in a level-triggered JK latch when \(J=K=1\) and the clock remains at its active level longer than the latch propagation delay. The intended equation is \(Q_{n+1}=\overline Q_n\), but the first toggle is fed back while the same clock pulse is still active, enabling the opposite input and causing another toggle. The output may change several times; its state when the clock closes depends on pulse width and propagation delay and is therefore unpredictable.

A master-slave JK flip-flop connects two level-sensitive latches in cascade and drives them with complementary clock phases:

1. While CLK is HIGH, the master accepts \(J,K\) and computes its state; the slave is disabled, so external \(Q\) cannot follow repeated internal changes.
2. When CLK goes LOW, the master is disabled and holds a fixed value; the slave becomes enabled and copies that value to \(Q\).
3. Since master and slave are never transparent together, the external output changes only once, effectively on the falling edge.

Race can also be prevented by shortening the active pulse below the round-trip propagation time, but that is poorly controlled. A true edge-triggered JK flip-flop is the usual modern solution because it samples only at a narrow edge. Master-slave designs can exhibit 1s catching if a brief active input is captured by the master during its transparent interval, another reason edge-triggering is preferred.

Practice target: 8 minutes; sketch the race waveform and explain the two non-overlapping master/slave phases in order.

Exam-ready answer

An excitation table is the inverse design form of a characteristic table: for a specified present state \(Q_n\) and required next state \(Q_{n+1}\), it lists the flip-flop inputs that will cause that transition. The symbol \(\times\) means don't-care and may be chosen as 0 or 1 during simplification.

The compact rules are \(D=Q_{n+1}\) and \(T=Q_n\oplus Q_{n+1}\). SR must never be assigned \(S=R=1\); JK has no forbidden combination.

Use in synchronous design: (1) list the required state sequence; (2) form a present-state/next-state table; (3) apply the excitation row separately to every state bit; (4) treat unused states and table \(\times\) entries carefully; (5) minimise each input column with Karnaugh maps; and (6) connect the resulting combinational logic to flip-flops sharing one clock.

For example, transition \(011\to100\) requires \(Q_2:0\to1\), hence \(J_2=1\); \(Q_1:1\to0\), hence \(K_1=1\); and \(Q_0:1\to0\), hence \(K_0=1\). Repeating this for every row creates the input maps. Finally, verify the realised equations by substituting every legal state and preferably assign unused states a recovery path rather than assuming don't-cares blindly.

Practice target: 8 minutes; reconstruct the combined table and translate at least one three-bit state transition into JK inputs.