Analog-to-Digital Conversion¶

Exam-ready answer

The sampling theorem states that a continuous-time signal strictly band-limited to a highest frequency \(f_m\) hertz can be reconstructed uniquely from uniform samples if

\(2f_m\) is the Nyquist rate of that signal, whereas \(f_s/2\) is the Nyquist frequency for a chosen sampler. Equality is an ideal limit; a practical system chooses \(f_s>2f_m\) to leave a transition band for a realizable filter.

Sampling by an impulse train produces shifted spectral replicas:

If \(f_s\geq2f_m\), adjacent replicas do not overlap and a reconstruction low-pass filter can select the baseband copy. If the condition is violated, replicas overlap and different analog frequencies produce the same samples. This irreversible folding is aliasing.

An input sinusoid then appears in the first Nyquist zone at

For example, sampling \(f_{in}=5.5\,\text{kHz}\) at \(f_s=8\,\text{kHz}\) gives the false component \(f_a=|5.5-8|=2.5\,\text{kHz}\).

Prevention: place an analog anti-alias low-pass filter before the sampler, limit its passband to the wanted \(f_m\), attenuate all components that could fold below \(f_s/2\), sample above the theoretical minimum, and provide a guard band for filter roll-off. Oversampling relaxes the analog filter and permits digital filtering/decimation, but it does not rescue frequencies already aliased at the sampling instant. A practical sample-and-hold then keeps each accepted sample constant during conversion; its finite aperture gives a sinc-like high-frequency droop and aperture jitter limits high-frequency SNR.

Practice target: 8–9 minutes; state both Nyquist terms, draw the separated/overlapped replicas, calculate one alias, and list the prevention chain.

Exam-ready answer

For a message strictly limited to \(|f|\leq f_m\), uniform sampling permits exact ideal reconstruction when

Sampling repeats \(X(f)\) around \(0,\pm f_s,\pm2f_s,\ldots\). When \(f_s<2f_m\), adjacent copies overlap and high-frequency content folds into the baseband; this is aliasing and cannot be removed digitally. Therefore the practical chain is analog anti-alias LPF \(\rightarrow\) sample-and-hold \(\rightarrow\) quantizer, with \(f_s\) chosen above \(2f_m\) to provide a guard band.

Companding means compression before a uniform quantizer and complementary expansion after decoding. Speech contains many weak samples, so a logarithmic compressor gives small input amplitudes relatively larger code spacing and improves their quantization SQNR; the expander restores the original amplitude law. It approximates nonuniform quantization without requiring a nonuniform binary ADC.

For normalized \(|x|\leq1\), the standard \(\mu\)-law characteristic is

It is used mainly in North America and Japan. The standard A-law characteristic is

and is common in European/international E1 telephony. A-law is linear very near zero and logarithmic above \(1/A\); \(\mu\)-law is logarithmic in one expression and gives somewhat stronger small-signal compression. Both improve low-level speech performance at the expense of deliberately nonuniform error versus input level; neither eliminates quantization noise. As a check, a \(3.4\,\text{kHz}\) telephone channel needs at least \(6.8\,\text{kHz}\) sampling, and the standard \(8\,\text{kHz}\) rate leaves a practical filter transition band.

Practice target: 9 minutes; reserve about 2 marks for sampling/aliasing and 3 marks for the companding chain, both laws, constants and regional use.

Exam-ready answer

A sample-and-hold (S/H) circuit captures the instantaneous analog input voltage and presents an approximately constant value to an ADC during its finite conversion interval. Its basic blocks are an analog switch, hold capacitor \(C_H\), high-input-impedance buffer and a sampling clock.

During sample/track mode, the clock closes the switch and \(C_H\) charges toward \(v_i(t)\) through the source and switch resistance; the buffered output follows the input. The acquisition time is the interval required to settle within the specified fraction of an LSB. At the sampling command the switch opens. During hold mode, the capacitor retains the captured charge and the buffer isolates it from the ADC load, so \(v_o\approx v_i(t_s)\) until conversion ends.

The circuit is necessary because comparator, SAR or integrating decisions take nonzero time. Without holding, the input could move while different bits are being decided, so one output word would correspond to several input values. The permitted input change is commonly kept below a fraction of one LSB, where \(1\,\text{LSB}=V_{FS}/2^n\).

Important specifications are: acquisition time; aperture delay, from command to actual disconnection; aperture jitter \(\sigma_t\), the uncertainty of that instant; droop rate, caused by leakage during hold; hold step/pedestal, caused by switch charge injection; feedthrough, unwanted input or clock coupling while held; and settling accuracy. For a sinusoidal input, timing uncertainty imposes approximately

For example, \(f_{in}=100\,\text{kHz}\) and \(\sigma_t=10\,\text{ps}\) give about \(104\,\text{dB}\); increasing input frequency by a factor of ten reduces this limit by \(20\,\text{dB}\). Flat-top holding also has an aperture sinc response, so aperture width and droop become important at high frequency or high resolution.

Practice target: 8–9 minutes; draw the switch-capacitor-buffer path, explain both clock states, and define at least five dynamic specifications.

Exam-ready answer

Quantization replaces every held sample by the nearest one of a finite number of amplitude levels. For an ideal \(n\)-bit uniform quantizer spanning \(V_{FS}\),

The encoder then assigns an \(n\)-bit word to the selected level. Sampling discretizes time; quantization discretizes amplitude.

Let \(x_q\) be the rounded level and \(e_q=x-x_q\). Except at overload, nearest-level rounding gives

For a sufficiently active input whose error samples can be modeled as uniformly distributed and uncorrelated over this interval, the mean error is zero and the mean-square noise is

Now take a full-scale bipolar sinusoid \(x(t)=V_p\sin\omega t\) over the range \(-V_p\) to \(+V_p\). Then \(V_{FS}=2V_p\) and

Hence

Converting the power ratio to decibels,

so

Thus every added bit ideally improves full-scale-sine SQNR by about \(6\,\text{dB}\). For \(n=8\), \(L=256\) and \(SQNR\approx49.92\,\text{dB}\). If \(V_{FS}=2\,\text{V}\), then \(\Delta=2/256=7.8125\,\text{mV}\) and the maximum rounding error is \(3.906\,\text{mV}\).

The result assumes an ideal uniform quantizer, no clipping, negligible thermal/jitter/nonlinearity noise, a full-scale sine, and a sufficiently decorrelated error. A sine below full scale has the same nominal step but less signal power, so its SQNR falls by the back-off in dB. Very small or periodic inputs can make error signal-dependent rather than white. Overload produces clipping error outside the \(\pm\Delta/2\) model. Nonuniform quantization or A/\(\mu\)-law companding improves weak-speech SQNR by using finer effective steps near zero, but does not change the stated ideal full-scale uniform result.

Practice target: 17–18 minutes; show the error integral, substitute the bipolar full-scale step, preserve power units, and finish with assumptions plus the 8-bit check.

Exam-ready answer

Part A — Principle of A/D conversion [3 marks]¶

An ADC converts a band-limited analog quantity into a finite binary word. The anti-alias filter first restricts input bandwidth; a sampler/S&H takes values at \(f_s\geq2f_m\) and keeps each value steady; the quantizer compares it with reference thresholds and chooses one of \(L=2^n\) levels; the encoder outputs the corresponding \(n\)-bit code. For span \(V_{FS}\),

for ideal nearest-level rounding. Resolution alone does not guarantee accuracy; reference, offset, gain, INL, DNL, noise and timing also matter.

Part B — Successive-approximation conversion [7 marks]¶

A SAR ADC uses one comparator, an \(n\)-bit DAC and a successive-approximation register to perform an MSB-to-LSB binary search on a held input.

1. A start-of-conversion (SOC) command freezes \(V_{in}\) in the S/H and clears/initializes the SAR.
2. The SAR tentatively sets the MSB, producing trial code \(100\ldots0\). The DAC generates \(V_{DAC}=V_{ref}/2\).
3. The comparator decides whether the trial is above or below \(V_{in}\). Retain the bit if \(V_{DAC}\leq V_{in}\); otherwise clear it.
4. Set the next bit provisionally, while keeping previous decisions, and compare again.
5. Continue to the LSB. After \(n\) comparisons the SAR latches the code and asserts end-of-conversion (EOC).

For straight binary weighting,

Four-bit example: let \(V_{ref}=16\,\text{V}\) and held \(V_{in}=10.4\,\text{V}\), so one LSB is \(1\,\text{V}\).

The final result is \(1010_2=10\), representing \(10\,\text{V}\) under this DAC convention. The search takes a fixed \(n\) decision clocks, independent of input magnitude, unlike a counter ADC whose delay may approach \(2^n-1\) clocks.

SAR offers a useful speed-resolution-power compromise and is common in microcontrollers, sensor interfaces and data acquisition. Its limitations are DAC settling and linearity, comparator offset/noise, reference error, capacitor/resistor matching and S/H acquisition/aperture error. The input must remain within the allowed error band for the complete search.

Practice target: 16–18 minutes; spend about 5 minutes on the 3-mark conversion chain and 11–13 minutes on the labeled SAR loop, trial table, fixed timing, merits and limits.

Exam-ready answer

All ADCs assign a held input to one of \(2^n\) codes, but their method of finding the code determines speed, hardware, noise rejection and resolution.

Flash ADC: a resistor string creates \(2^n-1\) thresholds. The same number of parallel comparators produce a thermometer code in one comparison interval, and a priority encoder converts it to binary. It is the fastest type, but area, power, input capacitance and offset-matching burden grow exponentially. For example, 8 bits require \(255\) comparators. It suits oscilloscopes, radar and very wideband acquisition.

Counter/digital-ramp ADC: a clocked binary counter drives a DAC. A comparator stops the count when \(V_{DAC}\geq V_{in}\); the count is the result. Hardware is simple, but conversion time depends on input and ranges from about one to \(2^n-1\) clocks. It is too slow for rapidly changing signals unless an S/H is used.

SAR ADC: one comparator, feedback DAC and SAR test trial codes from MSB to LSB. Each comparison halves the remaining range, so an \(n\)-bit result requires approximately \(n\) fixed decision cycles. It offers medium/high speed, moderate power and commonly medium/high resolution, making it the general-purpose choice for embedded and instrumentation work.

Dual-slope ADC: an integrator first integrates unknown \(V_{in}\) for fixed \(T_{int}\), then an opposite reference is applied until the output returns to zero. Charge balance gives

for consistent polarity magnitudes. The shared \(RC\) scale cancels, and selecting \(T_{int}\) as an integer number of mains periods strongly rejects \(50/60\,\text{Hz}\) interference. It is precise but slow, so it is used in digital multimeters and precision DC measurement.

Sigma-delta ADC: a subtractor, integrator, usually one-bit quantizer and one-bit feedback DAC run at a high oversampling rate. The loop noise-shapes quantization error toward high frequencies; a digital low-pass/decimation filter removes it and reduces sample rate. With \(OSR=f_s/(2B)\) it achieves very high resolution and linearity for audio/sensors, but has digital-filter latency and limited instantaneous signal bandwidth.

As a scale comparison, a 12-bit flash would need \(4095\) comparators; a 12-bit SAR needs about 12 comparisons; a counter may need 4095 clocks; a dual-slope may deliberately integrate for thousands of clocks; and sigma-delta trades a very high internal sample rate for a much lower, accurately filtered output rate. Therefore “fastest” is flash, “balanced general purpose” is SAR, “best integrating precision” is dual-slope, and “highest narrowband resolution” is sigma-delta, subject to actual converter specifications.

Practice target: 18–20 minutes; give each conversion path and timing law, then reproduce the five-row comparison and one hardware-count example.

Exam-ready answer

A DAC maps an \(n\)-bit code \(D\) to a proportional analog voltage or current. Under one ideal unipolar convention,

so one ideal step is \(V_{ref}/2^n\) and full-scale code is one LSB below \(V_{ref}\). A zero-order-hold DAC output contains steps and switching images; a reconstruction low-pass filter recovers the wanted smooth waveform.

Binary-weighted resistor DAC: each bit switch connects a branch to \(V_{ref}\) or ground. Branch resistors \(R,2R,4R,\ldots,2^{n-1}R\) produce currents weighted \(1,1/2,1/4,\ldots\), and an op-amp sums them. For an inverting four-bit design with feedback \(R_f=R\),

up to the circuit's chosen scaling. It is direct and fast, but high resolution requires a very wide range of precisely ratioed resistors and negligible switch resistance.

R-2R ladder DAC: every section uses only \(R\) and \(2R\). Looking into each ladder node gives the same equivalent resistance, so current divides by two successively and creates binary weights. Switches steer each bit to reference or ground and an op-amp sums the ladder output. Only a 2:1 resistor ratio must match, making IC fabrication, scaling and switch loading better than the simple weighted network; finite matching still limits INL/DNL.

Current-steering DAC: matched unit or binary/segmented current sources are always on, while high-speed switches steer their currents to the output or a dummy node. A transimpedance/load converts total current to voltage. Thermometer-coded MSBs reduce major-carry glitches, while binary LSBs limit area. It is the fastest common DAC form for RF and waveform generation, but source mismatch, output compliance, clock skew and switching transients limit accuracy and spectral purity.

Important specifications are: resolution, one LSB; accuracy, total closeness to ideal; offset error, output at zero code; gain error, slope/full-scale error after offset removal; DNL, actual step minus one ideal LSB; INL, deviation from the ideal transfer line; monotonicity, output never decreases as code increases; settling time, time after a code change to enter and remain inside a stated error band; glitch impulse, transient energy during unequal switch timing; and output noise/temperature drift. \(DNL>-1\,\text{LSB}\) is a common sufficient monotonicity condition.

Example: for an ideal 8-bit, \(V_{ref}=5.12\,\text{V}\) DAC, one LSB is \(5.12/256=20\,\text{mV}\). Code \(D=160\) gives \(V_o=5.12(160/256)=3.20\,\text{V}\). A real result must also be checked against INL, DNL, gain, settling and load specifications; nominal resolution alone is not accuracy.

Practice target: 18–20 minutes; draw the two resistor networks, explain current steering, state the ideal transfer/example, and define at least eight specifications.