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NMOS / CMOS Logic Circuits - TikZ Figures

Depletion-load NMOS inverter Y= A, NAND Y=AB with a series PDN, and NOR Y=A+B with a parallel PDN. Each load has its gate tied to source and is always conducting
Fig: Depletion-load NMOS inverter Y= A, NAND Y=AB with a series PDN, and NOR Y=A+B with a parallel PDN. Each load has its gate tied to source and is always conducting
CMOS inverter and its two stable current-path states
Fig: CMOS inverter and its two stable current-path states
Representative CMOS inverter VTC. The dashed line locates V_I=V_O; its intersection gives the switching point V_M
Fig: Representative CMOS inverter VTC. The dashed line locates V_I=V_O; its intersection gives the switching point V_M
Complementary two-input CMOS networks: NAND uses a parallel PMOS PUN and series NMOS PDN; NOR uses a series PMOS PUN and parallel NMOS PDN
Fig: Complementary two-input CMOS networks: NAND uses a parallel PMOS PUN and series NMOS PDN; NOR uses a series PMOS PUN and parallel NMOS PDN
CMOS transmission gate with complementary control
Fig: CMOS transmission gate with complementary control