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Technical Diagram Audit (Historical Record)

Audit date: 2026-07-28
Completion date: 2026-08-02 Scope: all 55 current chapters under 03_technical/, their question maps, answer plans, body text and referenced visual assets. Goal: make every required exam visual reproducible by hand, technically correct, and directly useful for scoring.

[!IMPORTANT] The current technical tree contains 55 note files after the Signals, Communications, and EDC chapter splits. This audit uses the current tree.

1. Completion Status

The initial audit found a coverage and specificity mismatch, not merely a low image count:

  • A question says "draw," but the answer has prose only.
  • A generic flow exists, but the question needs a real architecture with interfaces.
  • A circuit exists, but the required timing chart or characteristic is absent.
  • A plot exists, but it omits the construction marks, operating points, or labels.
  • An exact multi-part PYQ has visuals for only one limb.

The audit treats one required exam visual as one visual package. A package may need two SVGs, such as a circuit plus its waveform.

All 160 tracked backlog rows are now resolved:

Priority Complete Source-limited Unresolved
P0 25 1 0
P1 100 0 0
P2 34 0 0
Total tracked packages 159 1 0

The source-limited P0 row is the NTC 2081 root-locus question: the available paper prints a symbolic \(\sigma\) and supplies no numerical value. Its figure therefore presents the complete symbolic construction without inventing a parameter. These are exam-scoring visual obligations, not unique image-file counts; shared concepts use one builder with chapter-local owners where needed.

Priority

  • P0: exact observed PYQ, especially NTC 2079/2081/2082.
  • P1: core 5- or 10-mark syllabus answer where the visual earns distinct marks.
  • P2: useful enrichment, comparison, or predicted variant.
  • W: a related SVG exists but is incomplete, unsafe, or too generic.
  • M: no adequate SVG is referenced.
  • C: complete and referenced in the current owning chapter.
  • S: source-limited completion; the available source does not support a numerical claim.

2. Diagram Quality Contract

A diagram is complete only when a student can redraw it without inventing missing information.

Every block diagram must show

  1. A clear left-to-right or top-to-bottom signal direction.
  2. Input and output names, including units or domains where relevant.
  3. Functional block names, not vague labels such as "process" or "unit."
  4. Every feedback path, summing sign, take-off point, and control input.
  5. Important interfaces or signals on connecting arrows.
  6. A short equation or operating condition only where it earns a mark.
  7. Enough spacing for labels to remain readable in mobile, print, and dark mode.

Use the correct visual type

Question demand Required visual
"Draw the block diagram" Functional blocks, interfaces, and signal flow
"Construction and working" Labeled physical or circuit construction
"Characteristics" Axes, operating regions, key points, and direction
"Timing / switching / coding" Aligned input, clock, state, and output waveforms
"Derive boundary condition" Pillbox/loop construction plus vector components
"Design a counter" State graph/table, minimized logic, circuit, and timing
"Compare modulation" Waveforms and spectra or constellations, not prose alone

Current static-asset policy

  • The former SVG generator was retired on 2026-08-06. Existing SVG files are frozen static artifacts retained for current notes.
  • New and replacement technical figures must be source-verified, high-DPI textbook PNG crops; do not recreate the Python or JavaScript generator.
  • Keep conventional symbols, labels, polarity, signal direction and equations identical between the source figure and the note.
  • Verify every crop at desktop/mobile width and exclude unrelated page text, headers and neighboring figures.

3. P0 Completion Record: Exact Questions First

Rank Exact demand Completion
1 NTC 2081 root-locus construction The source scan verifies a symbolic \(\sigma\), not a number. Added an explicitly source-limited symbolic construction with poles, conditional segment, centroid, asymptotes, breakaway polynomial and departure expression; no numerical locus is claimed.
2 NTC 2079 VHF antennas Added folded dipole, labeled Yagi, gain-improvement methods, and the parabolic-reflector feasibility argument in one answer package.
3 NTC 2081 magnetic boundary conditions Added the infinitesimal pillbox and Amperian loop used in the derivation.
4 NTC 2082 two-bit counter Corrected the falling-edge convention and added aligned CLK, Q0, Q1, state sequence, and ripple-delay timing.
5 NTC 2081 controlled rectifier Added the four-SCR full-wave bridge, firing pulses, conducting pairs, and delayed output waveform.
6 NTC 2079 PCM transmitter/receiver Completed both chains with channel, line coding/decoding, 3R regeneration, clock recovery, and 64 kbps annotations.
7 NTC 2082 DS-SS/FH-SS and DS-CDMA Added spreading/hopping comparison plus acquisition and early-prompt-late tracking loops.
8 NTC 2079 system bus Added CPU, memory, and I/O on correctly directed address, data, and control buses.
9 NTC 2082 cache memory Added tag lookup, hit path, miss fetch, line fill, locality example, hit ratio, and AMAT inset.
10 NTC 2081 optical transmitter/receiver Added full Tx/Rx functional blocks, PIN/APD alternatives, TIA, equalization, decision and clock recovery.
11 NTC 2082 fiber types Extended the figure with cross-sections and refractive-index profiles for all three types.
12 NTC 2079 satellite/Kepler Added ellipse/focus, apogee/perigee, equal-area sectors, and the period-major-axis law.
13 NTC 2081 satellite link factors Added an uplink/downlink gain-loss chain with EIRP, path/rain/pointing loss, transponder gain, receive G/T, and combined C/N0.
14 NTC 2081/2082 protection Completed the site layout, earthing/shielding constructions, shock-protection devices, bonding, and surge-current paths.
15 NTC 2082 dipole/polarization/matching/skin depth Corrected principal-plane labels and added polarization loci, mismatch angle, matching methods, and the 5 MHz copper skin-depth construction.
16 NTC 2082 control composite Kept the complete open/closed-loop figures and added a pole-zero stability map with response thumbnails.
17 NTC 2082 AC composite Referenced three_phase_phasors.svg and star_delta.svg together and added full resistance-conversion formulas.
18 NTC 2082 cloud plus algorithm/flowchart Kept the exact port flowchart and added the cloud service/deployment architecture and answer section.

4. EDC and Digital Logic Backlog

EDC visual policy supersedes the SVG rows below

The EDC section was migrated on 2026-08-06 to source-verified, high-DPI textbook PNGs from Boylestad, Sedra/Smith, Floyd and Maini. All 114 EDC catalog SVG owners and outputs were removed; no EDC Markdown page references an SVG.

The tables in this section retain the former SVG names only as a historical coverage specification. They must not be recreated. For current work, locate the corresponding *_textbook.png in the chapter img/ folder, verify it against the source PDF, and follow .github/instructions/figure-crop.instructions.md.

01_edc/01-bjt/ and 01_edc/02-fet/

No open diagram item is currently listed.

01_edc/01_logic_families.md

State Topic Proposed SVG Required content
C/P1 NMOS versus CMOS inverter nmos_cmos_inverter_vtc.svg Paired VTCs; NMOS ratio-dependent levels/static current versus CMOS rail-to-rail levels, switching point, thresholds, and noise margins.
C/P1 NAND/NOR as universal gates universal_gate_realizations.svg NAND-only and NOR-only NOT, AND, and OR; tied inputs, intermediate complements, and Boolean result under each circuit.

01_edc/03-op-amp/

State Topic Proposed SVG Required content
C/P1 Ideal op-amp and virtual ground ideal_opamp_virtual_ground.svg Pin/rail labels and ideal properties; separate negative-feedback panel showing a virtual node that is not physically grounded.
C/P1 Inverting/non-inverting amplifiers opamp_inverting_noninverting.svg Complete resistor networks, feedback path, virtual node, current direction, and both closed-loop gains.
C/P2 Summing, differential, integrator, differentiator opamp_application_circuits.svg Four compact circuits with polarities and governing equations.

01_edc/07-amplifier/

State Topic Proposed SVG Required content
C/P1 Coupling methods amplifier_coupling_methods.svg RC, direct and transformer interstage paths with DC transfer, matching and bandwidth trade-offs.
C/P1 CE RC-coupled amplifier rc_coupled_ce_amplifier.svg Complete divider bias, input/output coupling, emitter bypass, load and voltage/current/power-gain relations.
C/P1 CE frequency response rc_coupled_frequency_response.svg Low/mid/high regions, \(f_L\), \(f_H\), -3 dB points, bandwidth and physical roll-off causes.
C/P1 Transformer push-pull transformer_coupled_push_pull.svg Centre-tapped phase splitter and output transformer, alternate Class-B paths and ideal efficiency limit.
C/P1 Push-pull crossover distortion push_pull_crossover_class_ab.svg Class-B stage, input/output dead-zone waveform, and two-diode Class-AB bias remedy with quiescent-current path.
C/P1 Class-C tuned amplifier class_c_tuned_amplifier.svg Biased transistor, collector tank/RFC/load, narrow current pulses, restored sinusoidal output, and resonance condition.
C/P2 Miller effect miller_effect_equivalent.svg Bridging capacitance, inverted gain, equivalent input/output capacitances, and high-frequency cutoff consequence.
C/P1 Negative-feedback amplifier negative_feedback_block.svg Signed summer, error, amplifier A, sampler beta, return path, and Af = A/(1+Abeta).
C/P1 Four feedback topologies feedback_topologies.svg Series/shunt input mixing versus voltage/current output sampling; gain type and impedance effects.
C/P1 Standard Bode responses standard_bode_responses.svg Magnitude and phase for low-pass, high-pass, band-pass and band-stop responses.
C/P1 Bode gain/phase margins Re-emitted bode_margins.svg Magnitude/phase panels with 0 dB, -180 degrees, gain/phase crossover, and GM/PM arrows. The former one-pole plot was insufficient.

01_edc/08-oscillator/

State Topic Proposed SVG Required content
C/P1 Oscillator feedback loop oscillator_feedback_loop.svg Noise seed, forward gain, amplitude control, selective positive return, startup and steady-state conditions.
C/P1 Wien bridge wien_bridge.svg Non-inverting amplifier, series/parallel RC bridge and independent gain-setting negative feedback.
C/P1 RC phase-shift oscillator phase_shift_oscillator.svg Inverting amplifier, three RC sections, feedback direction, phase contributions, gain condition, and frequency.
C/P1 Colpitts and Hartley colpitts_hartley_transistor.svg Actual paired transistor circuits with bias/supply, tapped capacitors or inductors, output, feedback arrows, and effective component formulas.
C/P2 Clapp oscillator clapp_oscillator.svg Colpitts-derived circuit with series C3, component hierarchy, tap, and equivalent capacitance.
C/P1 Series/parallel resonance series_parallel_resonance.svg Both topologies and characteristics: series current peak/impedance minimum, parallel line-current minimum/impedance maximum, bandwidth and Q.
C/P1 Quartz crystal quartz_crystal_equivalent_response.svg Motional RLC branch in parallel with holder capacitance plus impedance curve at series and parallel resonance.
C/P1 Pierce crystal loop pierce_crystal_oscillator.svg Inverting active stage, crystal, load capacitors, bias resistor and load-capacitance relation.
C/P1 PLL pll_block.svg Phase detector, loop filter, VCO, negative feedback and lock path for the retained communication PYQ.

01_edc/02_semiconductor_memory.md

State Topic Proposed SVG Required content
C/P1 SRAM versus DRAM sram_dram_cells.svg 6T SRAM with BL/BL-bar/WL and 1T1C DRAM with storage node, read, refresh, and destructive-read labels.

01_edc/04-anlg-filters/00_analog_filters.md

State Topic Proposed SVG Required content
C/P1 Active low-pass filter active_low_pass_filter.svg First-order op-amp circuit plus response with cutoff, -3 dB, and roll-off.

01_edc/05-ad-conv/

State Topic Proposed SVG Required content
C/P1 SAR ADC sar_adc_complete.svg Add reference, clock, start/end conversion, correctly directed DAC loop, and a four-bit trial-code/DAC staircase timing panel.
C/P1 Flash and dual-slope ADC flash_adc.svg, dual_slope_adc.svg Ladder/comparator/priority encoder; switched integrator/comparator/counter with fixed run-up and measured run-down.
C/P2 Sigma-delta ADC sigma_delta_adc.svg Summer, integrator, one-bit quantizer/DAC loop, bitstream, digital filter/decimator, oversampling, and noise-shaping note.

01_edc/06-powr-ex/

State Topic Proposed SVG Required content
C/P1 SCR two-transistor analogy scr_two_transistor_analogy.svg Cross-coupled PNP/NPN, terminal/current labels, gate injection, regenerative path, and latching condition.
C/P0 Full-wave controlled rectifier scr_full_wave_controlled_rectifier.svg Four-SCR bridge, AC/load labels, diagonal conducting pairs, gate pulses at alpha and pi+alpha, and output intervals.
C/P1 Seven-segment drive seven_segment_ca_cc_driver.svg Common-cathode/7448 active-HIGH versus common-anode/7447 active-LOW paths, current resistors, BCD bus, and segment labels.

01_edc/06_digital_logic/00_combinational_arithmetic.md

State Topic Proposed SVG Required content
C/P1 Four-bit adder/subtractor four_bit_adder_subtractor.svg Four full adders, XOR-conditioned Bi, mode input, C0=M, carry path, outputs, add/subtract states, and overflow.
C/P1 Carry look-ahead carry_lookahead_4bit.svg Parallel generate/propagate block, all carry equations/outputs, sum inputs, and contrast with ripple carry.
C/P2 BCD adder bcd_adder.svg First sum, correction detector, conditional 0110 adder, BCD digit, and decimal carry.

01_edc/06_digital_logic/01_combinational_selection.md

State Topic Proposed SVG Required content
C/P1 Magnitude comparator magnitude_comparator_logic.svg One-bit logic plus cascaded 7485 stages and all three cascade lines.
C/P1 Parity generator/checker parity_generator_checker.svg XOR trees for even/odd generation and receiver error output with 0/1 interpretation.
C/P2 1-to-4 demultiplexer demux_1to4_logic.svg Data fan-out, four AND gates, select/complement distribution, outputs, and minterm labels.

01_edc/06_digital_logic/02_flip_flops.md

State Topic Proposed SVG Required content
C/P1 JK race-around jk_race_around_master_slave.svg Wide clock with repeated toggling at J=K=1; master/slave latches with complementary clocks and one transfer per cycle.

01_edc/06_digital_logic/03_registers_counters.md

State Topic Proposed SVG Required content
C/P0 Two-bit ripple counter ripple_counter_2bit.svg Uses an explicit falling-edge convention, correct interstage connection, aligned waveforms, 00-01-10-11 sequence, and propagation-delay markers.
C/P1 Synchronous mod-5 counter mod5_jk_kmaps.svg, mod5_jk_counter.svg, mod5_state_timing.svg Six K-maps with unused states, minimized JK circuit on a common clock, state loop, and verified timing.
C/P1 Ring versus Johnson counter ring_johnson_counters.svg Four-D-FF chains, normal versus complemented feedback, initialization, and compact 4-state/8-state strips.
C/P2 Bidirectional shift register bidirectional_shift_register.svg MUX before each D input, left/right neighbors, direction select, serial inputs, parallel outputs, and common clock.
C/P2 LFSR lfsr_4bit.svg Four-stage register, labeled primitive-polynomial taps, XOR feedback, seed, output stream, and all-zero lockout.

5. EMT, Control, and Basic Electricity Backlog

02_emt/00_electrostatics.md

State Topic Proposed SVG Required content
C/P2 Field lines and dielectric boundary electrostatic_field_boundaries.svg Charge/dipole field and equipotential sketches; dielectric interface with normal, surface charge, tangential E, and normal D relations.

02_emt/01_magnetostatics.md

State Topic Proposed SVG Required content
C/P1 Biot-Savart and Ampere constructions ampere_biot_savart_constructions.svg Current element to observation point, straight-wire loop, solenoid rectangle, and toroid path with vectors/enclosed current.
C/P0 Magnetic boundary derivation magnetic_boundary_derivation.svg Infinitesimal pillbox and rectangular loop, dimensions, path direction, normal B, tangential H, surface current, and limiting integrals.

02_emt/02_wave_propagation.md

State Topic Proposed SVG Required content
C/P1 Uniform plane wave and normal incidence uniform_plane_wave_boundary.svg Right-handed E/H/k triad and in-phase traces; incident/reflected/transmitted fields at an impedance boundary with correct H directions.
C/P0 Skin effect at 5 MHz skin_effect_depth_5mhz.svg Current crowding in conductor, exponential depth curve, 36.8% at one skin depth, frequency trend, and copper result about 29.6 micrometres.
C/P0 Impedance matching impedance_matching_methods.svg Direct match, quarter-wave transformer, open/short shunt stub, antenna load, reflection coefficient, and SWR outcomes.

02_emt/03_antennas_waveguides.md

State Topic Proposed SVG Required content
C/P1 General radiation-pattern terms radiation_pattern_lobes.svg Main/side/back lobes, boresight, nulls, half-power points, HPBW, and FNBW.
C/P0 Half-wave dipole planes dipole_radiation_planes.svg Correct dipole, torus, E-plane figure-eight, H-plane circle, axial nulls, and broadside maxima.
C/P0 Polarization and mismatch antenna_polarization_mismatch.svg Linear/circular/elliptical loci, amplitude/phase conditions, handedness, Tx/Rx vectors, mismatch angle, and polarization loss factor.
C/P0 NTC 2079 VHF composite vhf_antenna_gain_ntc2079.svg Folded dipole; complete Yagi labels and main beam; director/boom/stacking gain methods; VHF dish-size feasibility equation.
C/P1 Rectangular waveguide TE10 rectangular_waveguide_te10.svg a>b section, propagation axis, TE10 E half-wave/H loops, field zeros/maxima, cutoff, evanescence, and lambda_c=2a.

03_control_system/00_system_fundamentals.md

State Topic Proposed SVG Required content
C/P2 Disturbance rejection disturbance_rejection_signed.svg Add disturbance-summer sign, negative-feedback sign, signal names, and disturbance transfer relation.

03_control_system/01_transfer_functions.md

State Topic Proposed SVG Required content
C/P0 Pole/zero significance pole_zero_stability_map.svg Poles and zeros across LHP, imaginary axis, and RHP; response thumbnails, dominant-pole distance, and RHP-zero inverse response.
C/P1 RLC and mass-spring-damper models physical_system_models.svg Fully labeled physical systems, defined input/output, force/voltage directions, and their transfer functions.
C/P1 DC motor model dc_motor_transfer_model.svg Armature block, torque constant, mechanical block, speed/position, integrator, and back-emf feedback.
C/P1 Reduction rules block_reduction_rules.svg Before/after pairs for cascade, parallel, both feedback signs, and moving summing/take-off points with G or 1/G.
C/P1 Worked block reduction block_reduction_worked.svg One valid nested system reduced in three visible stages with equivalent blocks and final transfer function.
C/P1 Mason signal-flow graph signal_flow_graph_mason.svg Directed nodes, two forward paths, loops, a non-touching pair, path/loop highlights, and explicit Mason substitution.
C/P1 Time-response specifications time_response_constructions.svg First-order 63.2%/time constant plus underdamped delay, rise, peak, overshoot, settling band, and settling time.

03_control_system/02_root_locus.md

State Topic Proposed SVG Required content
C/P1 Generic three-pole locus root_locus_three_pole_correct.svg Correct real segments, breakaway, centroid/asymptotes, complete branches, and arrows toward infinity.
S/P0 NTC 2081 symbolic locus root_locus_ntc2081_verified.svg The repository scan verifies \(G(s)H(s)=K/[s(s+\sigma)(s^2+4s+13)]\) and supplies no numerical \(\sigma\). The figure therefore shows symbolic poles, conditional real-axis segment, centroid, asymptotes, breakaway polynomial and departure expression, and explicitly disclaims a numerical locus.
C/P2 Design grid root_locus_design_grid.svg Constant damping-ratio rays, natural-frequency circles, settling-time line, desired pole, and pole/zero pull comparison.

03_control_system/03_frequency_response.md

State Topic Proposed SVG Required content
C/P1 Bode construction bode_construction_example.svg Stated transfer function, corner ledger, cumulative slopes, corrected magnitude, and summed phase.
C/P1 Polar/Nyquist construction polar_nyquist_construction.svg Positive-frequency polar trace, Nyquist contour/map, direction arrows, critical point, encirclement, and chosen sign convention.
C/P1 Second-order frequency response second_order_frequency_response.svg Magnitude curves by damping ratio, resonant peak/frequency, bandwidth, and phase transition.
C/P2 Lead/lag compensation lead_lag_bode_effects.svg Pole-zero order, phase bump/dip, crossover/bandwidth shift, and combined lag-lead case.

08_basic_electricity/00_circuit_analysis.md

State Topic Proposed SVG Required content
C/P1 Kirchhoff laws kirchhoff_laws.svg Current-labeled KCL node and source/resistor KVL loop with voltage polarities and loop direction.
C/P1 Mesh and nodal analysis mesh_nodal_examples.svg Two meshes with shared resistor and two current arrows; grounded node circuit; supermesh/supernode insets.
C/P1 Network theorems network_theorem_equivalents.svg Superposition source killing plus original, Thevenin, and Norton two-terminal equivalents with test quantities.

08_basic_electricity/01_ac_fundamentals.md

State Topic Proposed SVG Required content
C/P2 RMS/average/form/peak factors sinusoid_rms_average.svg One cycle, peak/period, half-cycle area, RMS/average levels, and factor formulas.
C/P1 AC through R/L/C ac_rlc_circuits_phasors.svg R/L/C rows with voltage-current phasors; series-RLC voltage and impedance triangles for lead/lag cases.
C/P1 AC power power_triangle.svg Lagging and leading triangles with P/Q/S, units, angle, power factor, and correction inset.
C/P1 Series/parallel resonance Reuse series_parallel_resonance.svg State practical topology assumptions and show both current/impedance characteristics, half-power frequencies, bandwidth, and Q.
C/P0 NTC 2082 composite three_phase_phasors.svg + star_delta.svg Both figures are referenced together and the answer includes complete star-to-delta and delta-to-star resistance-conversion formulas.

08_basic_electricity/02_machines.md

State Topic Proposed SVG Required content
C/P1 Transformer construction transformer_construction.svg Closed laminated core, limbs/yokes, both windings, load, voltage labels, and mutual flux path.
C/P1 DC generator construction dc_generator_construction.svg Yoke, poles/shoes, field coils, armature/winding, shaft/bearings, segmented commutator, brushes, load, flux, and rotation.
C/P1 DC motor principle dc_motor_principle.svg Field, armature-current directions, forces/torque, split commutator, brushes, supply, and opposing back emf.
C/P2 Induction versus synchronous machine ac_machine_construction_comparison.svg Three-phase stator, cage versus field rotor, speed/slip distinction, and start/damper note.

08_basic_electricity/03_protection.md

State Topic Proposed SVG Required content
C/P0 Complete telecom-site protection telecom_site_protection_complete.svg Retains lightning paths and includes isolator/MCB/RCCB, protective-earth-to-rack path, chassis bonding, and explicit surge-current arrows.
C/P0 Earthing and shielding earthing_shielding_constructions.svg Plate/pipe pits, backfill/test link, cable shield section, one-end LF versus both-end RF bonding, master earth bar, and loop warning.

6. Signals and Communication Backlog

04_signal_analysis/00_signals_classification.md

State Topic Proposed SVG Required content
C/P1 Standard signals Expand standard_signals.svg Add ramp to step, impulse, signum, and normalized sinc; label levels, impulse area, and sinc zeros.
C/P2 Classification examples signal_classification_examples.svg Compact paired sketches for continuous/discrete, periodic/aperiodic, even/odd, causal/two-sided, and energy/power examples.

04_signal_analysis/01_information_transmission.md

State Topic Proposed SVG Required content
C/P1 Baseband versus passband baseband_passband_spectra.svg Spectrum around zero versus translated copies around carrier, bandwidth braces, and mixer/carrier arrow.

04_signal_analysis/02_lti_convolution.md

State Topic Proposed SVG Required content
C/P1 Graphical convolution Replace convolution_graphical.svg Five stages: original, fold, shift, multiply/overlap at representative shifts, and complete piecewise output with support limits.

04_signal_analysis/03_transforms.md

State Topic Proposed SVG Required content
C/P1 Hilbert-transform SSB hilbert_ssb_generation.svg Message/Hilbert paths, quadrature carriers, product modulators, add/subtract USB/LSB, and cancellation labels.
C/P1 Sampling and aliasing sampling_aliasing_spectra.svg Time-domain samples plus separated and overlapping spectral replicas, anti-alias filter, and reconstruction path. Emit into both owning chapters.

04_signal_analysis/04_systems_filters.md

State Topic Proposed SVG Required content
C/P1 IIR Direct Form I iir_direct_form1.svg Separate feedforward and feedback delay lines, coefficient taps, output summer, and total delay count.

05_analog_digital_comm/00_communication_fundamentals.md

State Topic Proposed SVG Required content
C/P1 General communication system Repair comm_system_chain.svg Widen/multiline long boxes and inject noise through an actual summing node in the channel.
C/P2 Noise spectra noise_psd_comparison.svg White thermal, flicker, and band-limited PSDs with correct axes/bandwidth.
C/P2 FDM overview Re-emit fdm_spectrum.svg Labeled channels, guards, and total occupied bandwidth.
C/P2 TDM overview Re-emit tdm_frame.svg Repeating frames, user slots, frame boundary, and time axis.

05_analog_digital_comm/01_analog_modulation.md

State Topic Proposed SVG Required content
C/P1 Envelope-detector distortion Expand envelope_detector_waveforms.svg Correct tracking, too-large-RC diagonal clipping, and negative-peak clipping in aligned panels.
C/P1 AM/DSB/SSB/VSB forms am_variants_waveform_spectra.svg Under/exact/over-modulated envelope and spectra with carrier/sidebands and bandwidth braces.
C/P1 Analog modulation generation analog_modulation_generation.svg AM bias/product, balanced DSB-SC, filter-method SSB, VCO FM, and phase-modulator PM paths.
C/P1 FM spectrum and Carson rule fm_spectrum_carson.svg Bessel sidebands, narrow/wide FM comparison, significant-sideband span, and Carson bandwidth.
C/P1 Foster-Seeley/ratio detectors fm_foster_ratio_detectors.svg Paired center-tapped transformer/diode circuits, limiter requirement, center-frequency balance, and ratio-detector stabilizing capacitor.

05_analog_digital_comm/02_digital_conversion.md

State Topic Proposed SVG Required content
C/P0 PCM transmitter pcm_tx.svg Anti-alias LPF, sampler, quantizer, encoder, serializer/line coder, channel, and 8 kHz x 8 bit = 64 kbps.
C/P0 PCM receiver pcm_rx.svg Channel, 3R/clock recovery, line decoder, PCM decoder, DAC/hold, reconstruction LPF, and non-overflowing labels.
C/P1 DPCM Replace dpcm.svg Signed summer, quantizer/encoder, inverse quantizer, local predictor feedback, and mirrored receiver predictor loop.
C/P0 SAR ADC exact answer sar_adc_complete.svg The complete builder emits independently owned EDC and communication chapter-local copies.
C/P1 Sample and hold sample_hold_circuit_waveforms.svg Switch/capacitor/buffer plus clock, input, track/hold output, acquisition, aperture, hold step, and droop.
C/P1 Quantization quantization_staircase_error.svg Sampled signal/levels, staircase, transfer curve with step size, and error bounded by half a step.
C/P1 A-law versus mu-law companding_characteristics.svg Both normalized compressor curves against linear reference, near-zero enlargement, inverse expansion, and low-level step benefit.
C/P1 Delta/adaptive delta modulation dm_adm_blocks_errors.svg DM transmitter/receiver feedback integrators, one-bit steps, normal tracking, slope overload, granular noise, and ADM step control.
C/P1 Binary-weighted/R-2R DAC dac_binary_r2r.svg Two op-amp circuits, reference/ground switches, resistor values/current directions, and output equations.

05_analog_digital_comm/03_coding_error_handling.md

State Topic Proposed SVG Required content
C/P2 PCM timing and 3R pcm_timing_frame_3r.svg Distorted/recovered pulse rows, clock and decision instants, reshape output, sync word, and repeated channel slots.

05_analog_digital_comm/04_digital_modulation.md

State Topic Proposed SVG Required content
C/P0 BPSK/QPSK generation bpsk_qpsk_generation.svg Includes oscillator, splitter, explicit 90-degree shift, polar I/Q map, product modulators, summer, and constellations.
C/P1 16-QAM qam16_constellation.svg Four-by-four I/Q grid, Gray labels, decision boundaries, nearest-neighbor spacing, and 4 bits/symbol.
C/P2 PAM/PWM/PPM pam_pwm_ppm_waveforms.svg Shared message/clock with aligned natural/flat-top PAM, PWM, and PPM rows.
C/P2 MSK continuity msk_phase_continuity.svg Data/frequency states, continuous phase, modulation index, and a discontinuous BFSK comparison.
C/P2 DSSS/FHSS overview Share dsss_fhss_comparison.svg Spreader/despreader, PSD, synthesizer/hopping control, and time-frequency grid.
C/P2 Mixer mixer_frequency_conversion.svg RF/LO multiplier, sum/difference output spectrum, selected IF, and image frequency.

7. Telecom, Optical/Wireless, and ICT Backlog

06_telecom_advanced/00_transmission_fundamentals.md

State Topic Proposed SVG Required content
C/P2 Basic telecom network basic_telecom_network.svg Terminal/access, local exchange, metro aggregation, core transport, destination, separate control/signaling and OSS/NMS planes.

06_telecom_advanced/01_multiplexing_traffic.md

State Topic Proposed SVG Required content
C/P1 E1/PCM-30 frame e1_pcm30_frame.svg 125 microseconds, 32 eight-bit slots, TS0 framing, TS16 signaling, 30 voice slots, and 2.048 Mbps.
C/P1 WDM wdm_system_spectrum.svg Multi-wavelength transmitters, optical MUX, fiber/EDFA, DEMUX/receivers, and wavelength spectrum.

06_telecom_advanced/02_data_comm_networking.md

State Topic Proposed SVG Required content
C/P1 Circuit/message/packet switching switching_techniques.svg Dedicated path with phases, whole-message store/forward, and packet datagram/virtual-circuit routes.
C/P2 X.25 versus Frame Relay x25_frame_relay_architecture.svg DTE/DCE/PSE, SVC/PVC, stack placement, DLCI/CIR, and congestion-bit labels.

06_telecom_advanced/03_switching_signaling.md

State Topic Proposed SVG Required content
C/P1 Strowger/crossbar strowger_crossbar_switches.svg Two-motion selector and labeled crosspoint matrix with selected path.
C/P1 SPC exchange spc_exchange_architecture.svg Line/trunk interfaces, scanner/distributor/marker, switching network, CPU/memory, O&M, and separate speech/control paths.
C/P1 TS/ST/TST/STS digital_time_space_switching.svg Replace four stage-name-only SVGs with speech/control memory, space matrix, highway/time-slot routing example, and four stage arrangements.
C/P1 SS7 architecture/stack ss7_architecture_stack.svg SSPs, mated STPs, SCP, voice versus signaling links, and MTP/SCCP/ISUP/TCAP-MAP stack.
C/P1 ISUP call flow ss7_isup_call_flow.svg Origin/destination lanes with IAM, ACM, ANM, speech, REL, and RLC.

06_telecom_advanced/04_network_technologies.md

State Topic Proposed SVG Required content
C/P1 ISDN reference configuration isdn_reference_configuration.svg TE2/R/TA/S/NT2/T/NT1/U/LT/ET and BRI/PRI channel bars.
C/P1 ATM atm_cell_vp_vc.svg 53-byte cell fields/bit widths, payload, VP bundle, and VC switching.
C/P1 PDH versus SDH pdh_sdh_add_drop.svg Add E-carrier rates/demux factors; contrast with STM ring, ADM, DXC, regenerator, and protection.
C/P1 ADSL adsl_system_frequency_plan.svg CPE splitter/modem, copper loop, exchange splitter, POTS switch, DSLAM/IP core, and voice/up/down spectrum.

06_telecom_advanced/05_advanced_technologies.md

State Topic Proposed SVG Required content
C/P1 UMTS architecture Upgrade umts_architecture.svg UE, Node B, RNC, circuit/packet core nodes, subscriber database, and Uu/Iub/Iu interfaces.
C/P1 GSM architecture Upgrade gsm_architecture.svg BTS/BSC/MSC/GMSC/HLR/VLR/AuC/EIR/OSS, interfaces, and non-overlapping labels.
C/P1 GSM mobile-originated call gsm_mo_call_flow.svg Access, channel assignment, authentication/ciphering, TCH, interworking call setup, alerting, and connect.
C/P1 VoIP voip_protocol_architecture.svg SIP UAs/proxy/registrar, direct RTP/RTCP media, codec/jitter buffer, and protocol stack.
C/P2 RTP header rtp_header.svg Bit-accurate V/P/X/CC, marker/payload type, sequence, timestamp, SSRC, and CSRC fields.
C/P0 DSSS versus FHSS dsss_fhss_comparison.svg PN spreading/correlation and PSD; PN-driven synthesizer/hopping mixer and time-frequency grid, emitted into both owning chapters.
C/P0 DS-CDMA synchronization dscdma_synchronization.svg Acquisition correlator/threshold followed by early-prompt-late DLL, discriminator, filter, code NCO, and optional RAKE after lock.

07_optical_wireless/00_fiber_optics.md

State Topic Proposed SVG Required content
C/P0 Fiber types fiber_types.svg Core/cladding, ray path, and refractive-index profile for single-mode step, multimode step, and multimode graded index.
C/P1 Attenuation fiber_attenuation_dispersion.svg Loss versus wavelength with Rayleigh, OH peaks, IR rise, and 850/1310/1550 nm windows.
C/P1 Dispersion Include second panel above Input pulse, modal delays, broadened/overlapping output, and intermodal/intramodal labels.
C/P1 Optical link budget optical_link_budget.svg Tx power, connector/splice/fiber losses, engineering margin, receiver sensitivity, and rise-time RSS panel.

07_optical_wireless/01_optical_components.md

State Topic Proposed SVG Required content
C/P0 Optical transmitter/receiver optical_transmitter_receiver.svg Line coder/driver, LED/laser, coupler/fiber, PIN/APD, TIA, filtering/equalization, decision, and clock recovery.
C/P1 APD apd_photodiode.svg Absorption/multiplication regions, reverse bias, drift, and impact-ionization carrier cascade.
C/P1 OTDR otdr_block_trace.svg Laser/coupler/APD/timer plus trace with dead zone, slope, connector, splice, bend, break/end, loss, and distance.

07_optical_wireless/02_wireless_communication.md

State Topic Proposed SVG Required content
C/P2 Propagation mechanisms wireless_propagation_paths.svg LOS, ground/building reflection, rooftop diffraction, scattering, shadowing, delays, and Doppler direction.
C/P1 Cellular architecture/handover cellular_architecture_handover.svg MS/BTS/BSC/MSC/core, movement between cells, RSS crossover, threshold/hysteresis, hard/soft handover.
C/P2 Multiple access multiple_access_resources.svg FDMA bands, TDMA slots, CDMA shared resource/codes, and OFDMA time-frequency grid.

07_optical_wireless/03_satellite_communication.md

State Topic Proposed SVG Required content
C/P0 Kepler laws kepler_laws.svg Earth at focus, apogee/perigee, equal-area sectors for equal time, and T^2 proportional to a^3.
C/P0 Satellite link budget satellite_link_budget.svg Uplink/downlink EIRP, propagation/rain/pointing losses, transponder gain, receive G/T, and combined C/N0.
C/P1 Earth station earth_station_block.svg Complete Tx and Rx chains through HPA/LNA, up/downconversion, duplexer/dish, codec/modem, and monitoring/control.
C/P1 Stabilization/tracking satellite_stabilization_tracking.svg Spin/despun and three-axis spacecraft, reaction wheels/thrusters, station keeping, and az/el tracking servo.
C/P2 VSAT topology vsat_topologies.svg Star, mesh, and hybrid networks with hub/remotes and traffic direction.

09_ict/00_computer_architecture.md

State Topic Proposed SVG Required content
C/P0 System bus system_bus.svg CPU, RAM, and I/O controller on address/data/control buses; direction, widths, read/write, clock, interrupt, and reset.
C/P0 Cache hit/miss cache_hit_miss.svg CPU request, tag compare, hit return, miss fetch, line fill, locality example, hit ratio, and AMAT.
C/P1 Computer block diagram Repair cpu_block.svg CPU must exchange with memory/I/O through buses; output must not originate from memory and storage must use an I/O path.
C/P1 Microprocessor organization Upgrade current microprocessor figure Show internal ALU/register/control buses, address/data/control external pins, and memory/I/O connection.
C/P1 Instruction cycle cpu_register_transfer_cycle.svg PC/MAR/MDR/IR transfers, memory read, decode/control, ALU/ACC execution, write-back, and interrupt check.
C/P1 Virtual memory virtual_memory_paging.svg Virtual pages, TLB/page table, valid/frame bits, physical frames, page fault, disk, and reload.
C/P0 Cloud computing cloud_computing_architecture.svg Clients/internet, SaaS/PaaS/IaaS layers, virtualization and resources, plus public/private/hybrid deployment.
C/P2 Parallel/serial/RS-232 parallel_serial_rs232.svg Parallel/serial timing and DTE-DCE TXD/RXD/RTS/CTS/GND.

09_ict/01_programming.md

State Topic Proposed SVG Required content
C/P1 Standard flowchart symbols flowchart_symbols.svg Terminal, input/output, process, decision, flow line, and connector with one example label each.
C/P2 Process states Upgrade process_states.svg Add dispatch, timeout/preemption, I/O wait, event completion, exit, and arrow labels.

09_ict/02_networking.md

State Topic Proposed SVG Required content
C/P1 Network topologies network_topologies.svg Terminated bus, switched star, directional ring, partial/full mesh, and tree.
C/P1 OSI/TCP-IP placement Re-emit osi_tcpip_stack.svg Use the existing exam-ready stack locally instead of drawing another version.
C/P2 DNS resolution Repair dns_resolution.svg Client and recursive resolver; resolver queries root, TLD, and authoritative servers and caches the final answer.
C/P2 Hub/switch/router domains hub_switch_router_domains.svg Shared versus per-port collision domains, router-separated broadcast domains, and operating layers.

09_ict/03_cyber_security.md

State Topic Proposed SVG Required content
C/P1 CIA triad cia_triad.svg Confidentiality/integrity/availability with representative controls and failure examples.
C/P2 Defense in depth defense_in_depth.svg Internet, edge firewall, DMZ, IDS/IPS, internal firewall, LAN/servers, identity, endpoint, SIEM, and isolated backup zones.

8. Reuse and Generator Plan

Do not independently redraw the same concept in multiple folders. Define one builder and emit chapter-local SVGs where ownership differs.

Share these builders

Builder Emit to
sarAdcComplete() EDC converters and digital conversion
seriesParallelResonance() Oscillators/resonance and AC fundamentals
samplingAliasingSpectra() Transforms and digital conversion
dsssFhssComparison() Digital modulation and advanced telecom
existing Bode margins Amplifiers and control systems
existing FDM/TDM figures Communication fundamentals and telecom multiplexing
existing OSI/TCP-IP stack Telecom networking and ICT networking

Existing generated assets not currently useful enough to add

  • ttl_nand_block.svg: removed; the referenced transistor-level schematic is stronger.
  • ttl_nor.svg: removed after being superseded by the transistor-level NOR figure.
  • ttl_tristate.svg: removed after being superseded by the transistor-level tri-state figure.

9. Completed Rollout

Batch 1: repaired exact-PYQ visuals

Completed the highest-scoring repairs first:

  1. Two-bit ripple counter.
  2. PCM transmitter and receiver.
  3. Controlled full-wave rectifier.
  4. Magnetic boundary derivation.
  5. Root-locus source verification and redraw.
  6. Fiber-type profiles.
  7. BPSK/QPSK generation.
  8. Site protection.

Batch 2: added absent exact-PYQ packages

Added VHF antennas, DS-CDMA, system bus, cache, optical Tx/Rx, Kepler/link budget, cloud, pole-zero map, polarization/matching, and skin effect.

Batch 3: completed core P1 answer families

Completed the reusable families:

  • op-amp circuits and feedback;
  • ADC/DAC and sampling/quantization;
  • control block reduction, Mason graph, and frequency construction;
  • switching/signaling and legacy-network architectures;
  • optical test/components and earth station;
  • machines, circuit analysis, and AC phasors.

Batch 4: completed P2 enrichment

Added LFSR, Clapp, sigma-delta, classification examples, propagation paths, defense in depth, and the remaining predicted extensions after the exact and core answer visuals were complete.

10. Validation Gate for Every Figure Batch

  1. Use a source-verified, tightly cropped, high-DPI textbook PNG beside the owning Markdown page (see .github/instructions/figure-crop.instructions.md); do not recreate the retired SVG/Python figure generator.
  2. Wrap each image in a <figure markdown="span"> … <figcaption>Fig: …</figcaption> block that reuses the alt text.
  3. Confirm every Markdown reference resolves to the intended chapter-local image.
  4. Inspect the crop in forced-light mode for labels, arrows, clipping, and topology.
  5. Inspect representative pages in dark mode and at a narrow viewport.
  6. Check monochrome/print readability.
  7. Run make build (dead-link checking) and make audit.
  8. Mark a visual complete only after its owning answer can be written from the figure without consulting prose.

11. Acceptance Target

Diagram readiness is complete when:

  • all P0 packages are technically verified and referenced beside their model answers;
  • every "draw/sketch/show" instruction has the exact requested visual type;
  • no architecture is represented by generic stage names when interfaces earn marks;
  • every circuit with time-dependent operation includes its essential waveform or timing chart;
  • all counter/design answers include state, logic, circuit, and timing evidence;
  • shared figures live beside their owning page and are referenced consistently;
  • make audit and make build pass;
  • all 55 technical chapters have zero unresolved P0/P1 visual packages.