Phase-Locked Loop¶

Possible Exam Questions¶

Exam Questions and Answer Map

Describe the function and applications of a phase-locked loop in communication systems. [5] — [PYQ 2081]
Answer plan: Draw phase detector → loop filter → VCO with negative phase feedback → explain acquisition, lock and tracking → distinguish capture/lock range → state FM demodulation, synthesis, clock and carrier recovery.
Model answer: PLL Operation and Communication Applications

1. Definition¶

A phase-locked loop (PLL) is a negative-feedback control system that adjusts an oscillator until the feedback phase tracks a reference phase. In lock, output and reference-related frequencies are equal and phase error is constant (or bounded in a digital detector).

2. Block Diagram¶

Fig: Textbook basic phase-locked-loop block diagram

Block	Function
Phase detector/PFD	Compares reference and feedback phase/frequency and produces error information
Loop low-pass filter	Removes detector ripple/noise and sets bandwidth, damping and acquisition dynamics
VCO/NCO	Converts control signal into output frequency/phase
Optional divider \(N\)	Divides output before comparison for frequency synthesis

3. Basic Equations¶

Near lock, an analog phase detector can be linearised as

\[ v_d=K_d(\phi_r-\phi_f). \]

The filtered control \(v_c\) tunes the VCO:

\[ \omega_o=\omega_{free}+K_vv_c. \]

Because phase is the integral of angular frequency, the VCO contributes an integrator \(K_v/s\) in a small-signal phase model. Loop-filter design is therefore central to damping and stability.

4. Operating Sequence¶

Free Running¶

Without a reference/control correction, the VCO oscillates near \(f_{free}\).

Acquisition/Capture¶

Reference and feedback differ in frequency/phase. The detector produces a varying error whose low-frequency component drives the VCO toward the reference-related frequency.

Lock¶

For unity feedback,

\[ \boxed{f_o=f_r}. \]

The phase difference settles to the value needed to generate the required VCO control voltage.

Tracking¶

Once locked, slow reference changes or VCO disturbances create phase error; negative feedback corrects the output so it follows within loop bandwidth.

5. Capture and Lock/Hold Ranges¶

Capture range: range of initial input frequencies from which the loop can acquire lock under stated conditions.
Lock/hold/tracking range: range over which an already locked loop remains locked.

Normally capture range is no wider than hold range. Exact values depend on detector, loop filter, VCO tuning range, signal level and acquisition method; a single universal formula does not apply to every PLL.

6. Frequency Synthesis¶

With divide-by-\(N\) in feedback, lock requires

\[ \frac{f_o}{N}=f_r, \]

so

\[ \boxed{f_o=Nf_r}. \]

A programmable divider selects channels. Fractional-\(N\) architectures obtain finer spacing but introduce quantisation/spur considerations.

7. Communication Applications¶

FM Demodulation¶

Within tracking range, VCO control voltage follows instantaneous input-frequency deviation; after scaling/filtering it is the recovered message.

Carrier Recovery¶

A PLL or Costas loop regenerates carrier phase for coherent PSK/QAM/DSB-SC detection.

Clock Recovery¶

Timing transitions from received data steer the oscillator, producing a sampling clock aligned to the data eye.

Frequency Synthesis¶

Reference plus programmable divider generates stable RF local-oscillator channels.

Jitter/Noise Filtering¶

The loop tracks low-frequency phase variation within bandwidth and attenuates selected high-frequency input jitter, while VCO noise dominates differently outside bandwidth.

8. Loop-Bandwidth Trade-Off¶

Wider bandwidth: faster acquisition/tracking, but more reference/detector noise passes and stability margin may decrease.
Narrower bandwidth: better high-frequency noise filtering, but slower capture/tracking and greater sensitivity to VCO drift outside the band.
Adequate phase margin/damping avoids ringing, cycle slipping and loss of lock.

9. Advantages and Limitations¶

Advantages¶

automatic frequency/phase tracking;
accurate synthesis from a stable reference;
narrowband carrier/clock extraction;
useful demodulation and jitter filtering;
easy digital programmability.

Limitations¶

finite capture and hold ranges;
acquisition time and possible false lock/cycle slips;
phase noise, reference spurs and divider noise;
loop-filter stability trade-offs;
VCO tuning nonlinearity and supply sensitivity.

Exam Traps

A PLL is a negative-feedback phase-control system, although it contains an oscillator.
Lock means equal reference-related frequency plus a controlled phase relationship, not necessarily zero phase error.
Capture range and hold range are not the same.
With divider \(N\), compare \(f_o/N\) to \(f_r\).

Rapid Recall¶

Blocks: detector/PFD → LPF → VCO → feedback.
Unity lock: \(f_o=f_r\).
Divide-by-\(N\): \(f_o=Nf_r\).
Capture first; hold/track after lock.
Uses: FM demod, synthesis, carrier recovery, clock recovery.

Model Answer — PLL Operation and Communication Applications [5 marks, PYQ 2081]¶

Exam-ready answer

A phase-locked loop is a negative-feedback system that adjusts an oscillator until its feedback phase tracks a reference and the reference-related frequencies are equal.

The phase detector/PFD compares reference and feedback phase/frequency and produces error. The low-pass loop filter removes detector ripple/noise and sets bandwidth, damping and acquisition speed. The VCO changes frequency according to control voltage, \(\omega_o=\omega_{free}+K_vv_c\).

Initially unlocked, detector error steers VCO frequency toward reference. In unity-feedback lock, \(f_o=f_r\) with the constant phase error needed for control. The loop then tracks slow changes. Capture range is where lock can initially be acquired; hold/lock range is where an already locked loop remains locked and is normally wider.

Applications are FM demodulation, carrier recovery for coherent detection, clock/data recovery, jitter filtering and frequency synthesis. With divide-by-\(N\) feedback, \(f_o/N=f_r\), hence \(f_o=Nf_r\). Loop bandwidth trades fast tracking against noise rejection and adequate phase margin is required.

Practice target: 8 minutes; draw the three main blocks and feedback path, explain free-run/capture/lock/tracking, then state four communication applications and divide-by-\(N\) synthesis.