Computer Architecture¶

Exam-ready answer

(a) Definition [1 mark]¶

A system bus is the shared set of electrical signal paths that interconnects the CPU, main memory and I/O controllers so that they can exchange addresses, data and timing or command information. A complete transfer needs all three logical groups: the address identifies the source or destination, the control lines state the operation and timing, and the data lines carry the value.

(b) Types of system bus [4 marks]¶

For a memory read, the CPU places an address on the address bus, asserts MEMORY READ, and waits for the selected memory to drive the data bus; a ready signal may end the cycle. For a write, the CPU places both address and data on their buses and asserts MEMORY WRITE. An interrupt travels from an I/O device toward the CPU, whereas an interrupt acknowledge travels back, illustrating why the control bus is mixed-direction.

Example: a byte-addressable processor with a 16-bit address bus can select

If its data bus is 8 bits wide, one byte moves per transaction; a 32-bit word requires four such transfers unless the interface supports a wider path. Bus width alone does not determine clock rate or total performance: arbitration delay, memory wait states, electrical loading and shared-bus contention can all reduce throughput. A fault on a shared address or control line may also affect every attached device, so systems use buffering, parity/error detection, access arbitration and timeouts where reliability is important.

Practice target: 8–9 minutes; allocate one mark to the definition, draw the labeled bus figure, and state direction, function and width effect for all three buses.

Exam-ready answer

Cache memory is a small, fast semiconductor memory placed logically between the CPU and main memory. It keeps copies of recently or frequently used instruction and data blocks so that most CPU references can be served without waiting for slower DRAM. Modern systems normally use a hierarchy such as private L1 instruction/data caches, larger L2 cache and a shared L3 cache.

Its effectiveness follows locality of reference: temporal locality means a recently used item is likely to be reused, while spatial locality means nearby addresses are likely to be accessed soon. On a hit, the requested valid tag is found and data returns from cache. On a miss, a complete cache line is fetched from the next level, supplied to the CPU and installed for likely reuse.

If \(H\) is hit ratio, \(T_c\) cache lookup time and \(T_m\) additional main-memory time on a miss, average memory access time is

Example: for \(H=0.95\), \(T_c=2\,\text{ns}\) and \(T_m=60\,\text{ns}\),

instead of about \(60\,\text{ns}\) for every uncached DRAM access, an idealized twelvefold reduction. Performance still falls for compulsory, capacity or conflict misses; writes require write-through or write-back policy, and multicore systems need cache coherence. Poor-locality workloads and cache side-channel leakage are limitations, so designers combine suitable line size/associativity with isolation and coherence controls.

Practice target: 8–9 minutes; define cache and both localities, explain hit/miss, write AMAT, and calculate the numerical example.

5-mark answer and 10-mark extension

For 5 marks — write the memory-hierarchy core¶

A memory hierarchy is the layered organization of storage by access time, capacity, cost per bit and proximity to the CPU. No single technology is simultaneously fastest, largest, cheapest and non-volatile, so frequently needed information is copied upward into small fast levels while bulk information remains in larger slow levels.

Moving downward increases capacity and access time but decreases cost per bit; moving upward increases speed and cost per bit. Registers and cache are managed mainly by compiler/hardware, main and virtual memory by hardware plus the OS, and files by the OS and applications.

Add for a 10-mark variant — locality and AMAT¶

The hierarchy succeeds because programs exhibit temporal locality (recently referenced instructions/data tend to be reused), spatial locality (nearby addresses tend to be referenced) and sequential instruction access. Data moves between adjacent levels in blocks: cache lines between cache and RAM, pages between RAM and backing store, and file-system blocks between secondary storage and memory.

For one cache level, the average memory access time is

where \(T_{hit}\) is hit time, \(r_{miss}\) is miss rate and \(P_{miss}\) is the additional miss penalty. With \(T_{hit}=1\,\text{ns}\), miss rate \(=0.02\) and penalty \(=50\,\text{ns}\),

This illustrates why a small high-hit-ratio cache can make a large slow memory appear much faster. At the page level, a present page maps through the TLB/page table to a RAM frame; an absent valid page causes a page fault and disk/SSD service that is millions of CPU cycles slower. Virtual memory is therefore an address-management and protection facility, not a fast physical memory level.

The arrangement gives low average access time, economical capacity and process isolation, but it cannot remove all delays. Workloads larger than cache suffer capacity misses; random access defeats spatial locality; too few RAM frames cause page-fault thrashing; and sudden power loss destroys volatile levels. Error-correcting memory, access permissions, cache coherence, backups and replacement policies improve reliability and security but add hardware or software overhead.

Practice target: 9 minutes for the five-mark hierarchy or 17 minutes for the full answer; reproduce the pyramid, comparison and one AMAT calculation.

5-mark answer and 10-mark extension

For 5 marks — write the CPU-organization core¶

The central processing unit (CPU) is the programmable unit that fetches, decodes and executes machine instructions and coordinates memory and I/O. Its main parts are the ALU, which performs arithmetic, logic, shift and comparison operations; the control unit, which decodes instructions and issues timing/control signals; a high-speed register set; clocking; and internal address, data and control paths.

The basic cycle is: fetch the instruction addressed by PC into IR and advance PC; decode its opcode, operands and addressing mode; fetch operands if required; execute in the ALU, branch unit, memory or I/O unit; write back the result; then test pending interrupts before starting the next instruction.

Add for a 10-mark variant — register transfers and execution¶

For a fixed-length instruction, the fetch micro-operations may be written as

T0: MAR <- PC
T1: MDR <- Memory[MAR]; PC <- PC + instruction_length
T2: IR  <- MDR
T3: Decode IR.opcode, IR.mode and IR.operand fields

The control unit then calculates an effective address for direct, indirect, indexed or base-plus-offset addressing, requests the operand, selects the ALU operation, updates condition flags and enables the destination register or memory write. A typical logical instruction format is:

| opcode | addressing-mode | destination register | source/register/address field |

Example: for LOAD R1, [2000], decode identifies a memory-read operation and direct address 2000; the CPU performs MAR <- 2000, MDR <- Memory[MAR], then R1 <- MDR. For ADD R1, R2, both register values feed the ALU, the sum returns to R1, and zero/carry/overflow flags are updated. A branch replaces the sequential PC with its target only when its tested condition is true.

If an enabled interrupt is accepted, the CPU completes or precisely records the current instruction, saves PC and status, loads the handler address from an interrupt vector, services the event and restores context on return. Pipelined CPUs overlap stages of different instructions for throughput, but data, structural and control hazards can stall or flush the pipeline; this changes timing, not the logical fetch-decode-execute result. CPU performance is also limited by clock rate, memory latency, instruction-set design and available parallel execution units.

Practice target: 9 minutes for the five-mark core or 17–18 minutes for the full answer; include the register-transfer fetch sequence and one decoded instruction example.

Exam-ready answer

Virtual memory is a hardware-and-operating-system technique that gives each process a large, private logical address space independent of the amount and arrangement of physical RAM. In paging, virtual memory is divided into equal-size pages and RAM into same-size page frames. A virtual address has the bit format

| virtual page number (VPN) | page offset |

The MMU first searches the translation lookaside buffer (TLB). On a TLB miss it reads the process page-table entry, whose essential fields include frame number, present/valid bit, read/write/execute protection, referenced bit and dirty bit. The physical address is formed without changing the offset:

If a referenced, legal page is absent, a page fault traps to the OS. The OS validates the address, obtains a free frame or selects a victim, writes a dirty victim back if necessary, reads the required page from secondary storage, updates the page table/TLB and restarts the faulting instruction. An illegal address or forbidden access instead terminates/signals the process; it is not demand-paged in.

Example: with 16-bit virtual addresses and \(4\,\text{KiB}=2^{12}\)-byte pages, the offset is 12 bits and the VPN is 4 bits. Address 0x3ABC is VPN 0x3, offset 0xABC; if page 3 maps to frame 9, the physical address is 0x9ABC.

Paging lets programs exceed RAM, supports relocation, multiprogramming, shared pages and per-page protection. Its costs are page-table storage, translation overhead, internal fragmentation and very slow faults. If active working sets exceed RAM, repeated replacement causes thrashing; sufficient frames, locality-aware replacement and working-set control are therefore essential.

Practice target: 8–9 minutes; draw the paging path, preserve the offset in the address example, and list every page-fault handling step in order.

Exam-ready answer

Cloud computing is the on-demand delivery over a network of a shared pool of configurable computing resources such as servers, storage, platforms and applications. Resources can be rapidly provisioned and released with minimal provider interaction, are pooled among users, scale elastically and are measured for billing or control.

A typical request is authenticated at the portal/API, scheduled onto pooled virtualized or containerized resources, connected to storage/network services, monitored, scaled and metered. Benefits are rapid deployment, elasticity, broad access, resource sharing and reduced initial capital expense. Limitations include provider dependence, latency/outage risk, migration lock-in, unpredictable recurring cost and legal data-location requirements. Controls should include strong IAM and MFA, least privilege, encryption in transit/at rest, tenant isolation, logs, backups, key management and a clear shared-responsibility agreement; moving to cloud does not transfer all security responsibility to the provider.

Practice target: 10–11 minutes; define the essential characteristics, reproduce both three-row matrices, and give one application for every deployment model.