Fig: Three-bit Flash ADC: eight equal ladder resistors, seven thresholds and comparatorsFig: SAR feedback architecture and a representative four-bit DAC ladderFig: Four-bit SAR conversion process: each comparison halves the remaining intervalFig: Dual-slope converter and fixed-run-up/variable-run-down sequenceFig: First-order sigma-delta loop and oversampling/noise-shaping concept